Electronics Electrical AccessoriesTransistor
As the reduction of transistor dimensions to improve performance in CMOS technology reaches its theoretical limits, alternative device concepts and or materials are called for. Here we endeavor to integrate group III-V arsenide and especially InAs lateral nanowires into a normal CMOS layout, which are to serve as the n-channel in the transistors for a future CMOS technology based on novel channel materials. Selective area growth is employed. Currently, we are optimizing growth conditions of the nanowires and are assessing their suitability for advanced CMOS approaches.Up to now development efforts in nanoelectronics are focused on the reduction of power consumption. High integration densities nevertheless call for a more efficient thermal heating management. Conventionally used approaches for heat dissipation have already reached their limits and further improvements could be achieved only by alternative device concepts and novel system architectures. Metallic substrates are one possible solution. We have reported on the first successful fabrication of a Schottky diode on a GaN layer/Ag substrate. The aim of our work is to compare the material characteristics of GaN layers and III-N heterostructures deposited on a Ag/Si substrate to standard GaN layers and to demonstrate the potential of metal layer containing growth templates for (opto)electronic devices, which can operate at harsh conditions.T-gate structures are essential for the reduction of gate resistance in radio frequency (RF) transistors. They are one of the most effective methods to improve the device maximum oscillation frequency (fmax). However, further innovative solutions are called for to reduce Skin-effect losses and improve device performance as the structure sizes diminish and the operation frequencies of the devices become even higher. We developed innovative gate preparation solutions to optimize electrode forms for high frequency device operation. The approach leads to an increase in electrode surface area whilst the volume of the conductive material (usually gold) is minimized.