Consumer DRAM

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Density: 2Gb Organization: 256Mx8 Speed: H9, K0, MA Package: 78FBGA

The 2Gb DDR3 SDRAM Q-die is organized as a 32Mbit x 8 I/Os x 8banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1600Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset . All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V(1.425V~1.575V) power supply and 1.5V(1.425V~1.575V) VDDQ. The 2Gb DDR3 Q-die device is available in 78ball FBGAs(x8).