Consumer DRAM

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Density: 4Gb Organization: 512Mx8 Speed: K0, MA, NB Package: 78FBGA

The 4Gb DDR3 SDRAM E-die is organized as a 128Mbit x 4 I/Os x 8banks or 64Mbit x 8 I/Os x 8banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 2133Mb/sec/pin (DDR3- 2133) for general applications. 
The chip is designed to comply with the following key DDR3 SDRAM fea-tures such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset . All of the control and address inputs are synchronized with a pair of exter-nally supplied differential clocks. Inputs are latched at the crosspoint of dif-ferential clocks (CK rising and CK falling). 
All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-ion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ.
The 4Gb DDR3 E-die device is available in 78ball FBGAs(x4/x8).