TSMC 40nm Technology

The 40nm logic family includes Low Power (LP), General Purpose Superb (G) and low-power triple gate oxide (LPG) process options. All three processes offer multiple threshold voltage (Vt) core devices and 1.8V, 2.5V, 3.3V I/O options to meet different product requirements. The 40nm LP process provides double the gate density of the 65nm process with significantly lower power and manufacturing cost per die making it ideal for small footprint designs such as those used in cell phones, portable media players, PDAs and other handheld devices. The 40nm G processes provide more than twice the density at the same leakage and more than a 40 percent speed improvement compared to TSMC's 65nm process. The process targets PC, networking, and wired communication applications.

TSMC takes process technology performance to the next density and power level with the introduction of its 40nm process technology. The TSMC 40nm process combines the most advanced 193nm immersion photolithography, performance-enhancing silicon strains, and extreme low-k (ELK) inter-metal dielectric material to bring both performance and reliability to advanced technology designs. 
A robust Design ecosystem and related services that accelerate rapid adoption and fast time-to-tape out complete TSMC's 40nm process technology. The design ecosystem includes:
The design ecosystem includes: 
Prototyping:  Prototyping programs streamline the transition from first silicon to production and include TSMC's the QuickStartSM IP program, the Prototype Diagnostics Alliance and CyberShuttle® services.  CyberShuttle® services allow multiple customers to share the costs of a single mask set and prototype wafers on a pilot run.
Extensive IP  TSMC's 40nm design ecosystem includes foundry's most advanced IP, including standard cell, standard I/O, SRAM, high speed I/O, standard interfaces, data converters and more. The IP Alliance Program supports TSMC's extensive portfolio of silicon-proven third-party IP.
Process design kit (PDK) quality assurance:  TSMC 40nm PDKs cover the entire design flow from schematic entry, simulation, layout, and layout check to post-simulation. The six-stage automatic PDK quality assurance flow, with over 133 procedures, ensures consistent quality control and faster development lead-time. "Smart installation" and easy-to-follow tutorial simplify adoption. Well proximity effect (WPE) modeling, Monte Carlo simulation, and estimated parasitic RC device information for pre-simulation improves design accuracy.
Design for Manufacturability (DFM):  TSMC's 40nm (DFM) initiative goes beyond design rules and SPICE models, providing additional manufacturing variance data that is essential for achieving high yields at the nanometer level. A model-based approach and a rule-based approach are available for designer implementation, along with a DFM Data Kit (DDK) for third-party EDA tools and a TSMC DFM toolkit that includes advisories and utilities.