|Taiwan Semiconductor Manufacturing Company Limited|
|No Title||0.02 MB|
Electronics Electrical AccessoriesTransistor
The related half-node process, 80GC (1.0/3.3V), was released in the fourth quarter of 2006 and achieves superior standby and active power while reducing die area by more than 10%, depending on the non-shrinkable IP module ratio. The 80GC process can be used in many product applications covering the consumer products, network and computer segments. Nexsys® technology satisfies the power, performance and integration requirements of a broad application spectrum and includes high-performance, low-power, mixed-signal/RF, embedded DRAM, and non-volatile memory options. TSMC established the Nexsys® brand for its next-generation SoC process technology. The company's 90-nm technology is the first TSMC process to adopt this brand. Nexsys® technology offers a unique triple gate oxide option that facilitates three different oxide thicknesses on a single chip. The triple gate oxide feature removes design restrictions caused by various core/IO combination requirements and should lead to more innovative SoC designs. With 70-75% linear shrink and twice the performance improvement, compared to TSMC's 0.13-micron technology, Nexsys® 90nm process is poised to become the de-facto SoC process technology standard.
Since 2004, TSMC has manufactured Nexsys® 90nm process in its Fab12, a state-of-the-art 12-inch fab located in Hsinchu, Taiwan. In 2005, TSMC qualified the process in Fab14 in Tainan. There are hundreds of product tape outs and hundreds of thousands 12-inch wafer shipment. TSMC has also developed a design for manufacturing (DFM) methodology to achieve better yield performance through volume production data. TSMC achieves significant economic advantages by combining its 90nm process technology and 12-inch wafer manufacturing capabilities.